1. Field of the Invention
This invention relates generally to an electronic memory devices. More particularly, this invention relates to circuits for the extraction or reading of digital data from an electronic memory.
2. Description of Related Art
In present electronic memory devices an address is decoded into row addresses and column addresses. The row addresses activates word lines of a row within an array of memory cells. All the memory cells of the row are activated and the digital data is transferred through bit line connection to sense amplifiers for recovery. The column address are used to activate bit line switches for selecting which column is to transfer its recovered data to a data line sense amplifier for further conditioning and amplification. The output of the data line sense amplifier is applied to a data line latch for synchronization with an external clock. The output of the data line latch is transferred to a data output latch for transfer through an output driver circuit to external circuitry.
This read path is structured as a three layer pipeline. The first stage is from the word line access to the bit line switch selection. The second stage is the data line sense amplifier to the data line sense amplifier latch and the third stage is the data output latch.
The latency of an access of data is determined by the time from the presentation of an address to the presence of the data at the output of the driver circuit. The structure of the second pipeline stage allows for shortening of the stage to improve the data access. If the pipeline stages (especially the second pipeline stage) are not shortened then the minimum latency is determined by the long cycle applications where data for different word lines are accessed sequentially. However, if the pipeline stages are shortened then the data transmission time form the bit line sense to the data output latch at the third pipe line stage is limited by the maximum external clock rate.
Refer now to FIG. 1 for a more detailed discussion of a read data path of the prior art. Memory cells 5 are arranged in rows and columns to form the sub-arrays 10a, . . . , 10n. An address is decoded to form the word line addresses 15 and the bit line addresses 45 for selecting the desired rows and columns of the memory sub-array 10a, . . . , 10n. Each of the memory cells 5 of a selected word line 15 is activated and the digital data is transferred to the bit lines (BL00, . . . , BLmn). The bit line sense amplifiers 22a, . . . , 22n acquire, amplify, and condition the digital data. The bit line switches 32a, . . . , 32n are connected to the terminal ends of the bit lines BL00, BL00, . . . , BLmn, BLmn to receive the digital data from the bit line sense amplifiers 22a, . . . , 22n. Each of the bit line switches 32a, . . . , 32n are formed of a pair of metal oxide semiconductor (MOS) transistors (M1 and M2). The gates of the MOS transistors (M1 and M2) are connected to receive the bit line selection signals BS 55 from the column decoder 50. The column decoder is connected to the column decode control circuit 40, which receives a bit line sense amplifier ready signal 35 indicating the digital data present on the bit lines BL00, BL00, . . . , BLmn, BLmn has been sense, amplified, and conditioned for transfer from the memory array 25. The column address 45 is decoded and one of the desired bit line switch 32a, . . . , 32n is activated to transfer the digital data from the memory array 25 through the bit line switches 32a, . . . , 32n to the data line sense amplifier 60. The data line sense amplifier 60 further amplifies and conditions the digital data. The output of the data line sense amplifier 60 is connected to the input of the data line sense amplifier latch 65. The data lines sense amplifier 65 is a data storage element used to synchronize the digital data with an external clock for transfer to external circuitry.
The output of the data line sense amplifier 60 is transferred to the input of the data output latch 70. The data output latch 70 is a second data storage element used to retain the digital data during transfer of the digital data through an off chip driver 75 to a data output terminal DQ 80 and to external circuitry.
The bit line switches 32a, . . . , 32n form the boundary 30 of the first pipeline stage. The data line sense amplifier latch 65 forms the boundary of the second pipeline stage and the data output latch forms the boundary of the third pipeline stage. As noted above, the second pipeline stage can be shortened to minimize the latency of the first access of the digital data from the memory. Thus the performance of the memory system is limited by this first access. If the pipeline transmission time is reduced, then the performance of the memory system is determined by the maximum clock frequency that determines the minimum transmission time from the bit line sense amplifiers 22a, . . . , 22n to the output terminal DQ 80.
“A 9 Ns 16 Mb CMOS SRAM with Offset Reduced Current Sense Amplifier.” Seno, et al., Digest of Technical Papers: 40th ISSCC IEEE International Solid-State Circuits Conference, 1993, pp.: 248-249, 297 describes a 4-Mb×4 SRAM (static random access memory) with a current-mode nonequalized read data path. The read data path has an offset-reduced stabilized-feedback current sense amplifier and a quadrant-organization architecture.
U.S. Pat. No. 5,959,900 (Matsubara) illustrates a synchronous semiconductor memory having a register with an input gate and an output gate, for holding read-out data between the input gate and the output gate. An input gate control circuit controls an open/close of the input gate with a output switch feedback signal in the form of a one-shot pulse generated by an output gate control circuit for controlling an open/close of the output gate. The open/close, in synchronism with an output gate switch signal, so that only after the data held in the register has been transferred to an external of the register, the next data to be successively transferred from the read/write bus to the register is actually latched in the register.
U.S. Pat. No. 6,452,865 (Wolford) provides a single common symmetrical double data rate (DDR) synchronous random access memory (SDRAM) read data path structure and corresponding storage addressing scheme. The read data path structure implements both an N-bit interface and an (N/2)-bit interface to the DDR memory. The read data path structure uses a feedback loop of a lower data path to a higher data path in conjunction with the translation of the physical addressing of the data stored into a memory. The feedback loop and address translation mechanism is enabled for (N/2)-bit mode and disabled for N-bit mode.
U.S. Pat. No. 6,539,454 (Mes) describes an asynchronously pipelined SDRAM. The asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. The data is synchronized to the clock at the end of the read data path before being read out of the chip.